Weblog Evaluate: Sept. 28

Automotive digital twins; class members in SystemVerilog; AI reminiscence bottlenecks; MEMS gyroscopes.


Cadence’s Paul McLellan shares extra highlights from the current Sizzling Chips, together with some very massive chips and accelerators for AI and deep studying, new networks and switches, and cellular and edge processors.

Synopsys’ Marc Serughetti considers the completely different use circumstances for digital twins in automotive and the way they can assist decide the impression of software program on verification, check, and validation actions in addition to allow early {hardware} and software program integration and frontload testing.

Siemens’ Chris Spear discusses class member visibility in SystemVerilog together with what to do if you wish to restrict entry to members.

Rambus’ Steven Woo discusses the AI reminiscence bottleneck and different key takeaways from the AI {Hardware} Summit, such because the problem of creating {hardware} and software program that addresses a variety of workloads.

Arm’s Paul Williamson argues that real-time 3D content material would be the subsequent massive disruptor in client tech, increasing from leisure and gaming to areas akin to automotive, healthcare, industrial, building, and navigation.

Ansys’ Laura Carter factors to challenges for colour blind drivers and the way simulation can assist create extra user-friendly shows by predicting what colour blind individuals will see in response to quite a few elements, akin to show brightness, decision, distinction, and illuminance in ambient lighting situations.

Coventor’s Arnaud Mother or father explores modeling a MEMS-based whole-angle gyroscope that may very well be utilized in superior navigation purposes, akin to north discovering or useless reckoning navigation.

SEMI’s Mark da Silva particulars 5 key know-how phases important to implementing an autonomous manufacturing unit encompassing your complete semiconductor product life cycle, from front-end to back-end, and the trail for semiconductor firms to implement good manufacturing applied sciences.

Renesas’ Chiaki Seiji considers the challenges in porting purposes throughout Arm and RISC-V CPUs, together with tight coupling of {hardware} and purposes, various peripherals, and the opportunity of incompatible general-purposes applications akin to middleware.

Intel’s Jakob Engblom examines the Gadget Modeling Language (DML) that can be utilized to mannequin gadgets akin to a timer, serial port, interrupt controller, accelerator block, or Ethernet interface and argues for the productiveness advantages of a domain-specific language.

Western Digital’s Thomas Ebrahimi considers how massive 3D printing techniques might allow microfactories that provide a proximal, just-in-time possibility for manufacturing and counter world provide chain challenges.

And don’t miss the blogs featured within the newest Techniques & Design publication:

Expertise Editor Brian Bailey explains why, at a time when many items of an EDA movement are being fused collectively, stress is mounting to make it much more open and amenable to exterior extension and enhancement.

Siemens’ WeiLii Tan advises catching IP correctness issues early within the design movement.

Synopsys’ Mike Gianfagna appears at how knowledge facilities have undergone a elementary shift, each within the quantity of knowledge and the way it’s processed.

Renesas’ Andrew Cowell examines a single structure to handle the facility calls for of the various various kinds of processors in a knowledge heart.

Codasip’s Mike Eftimakis explores completely different configurations and combos of IP in a single surroundings.

Cadence’s Ben Gu argues that electromagnetic evaluation is important for interposer designs.

Jesse Allen

Jesse Allen

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Jesse Allen is the Information Middle administrator and a senior editor at Semiconductor Engineering.